1. Field of Invention
The present invention relates to a semiconductor device including a plurality of ferroelectric capacitors and a method for manufacturing the same. More particularly, the invention relates to technology useful for forming a plurality of ferroelectric capacitors of uniform dimensions.
2. Description of Related Art
As a larger scale integration and smaller configuration of a semiconductor device have been achieved in recent years, a cross-point FeRAM has drawn attention as a semiconductor device having ferroelectric capacitors. In the cross-point FeRAM, upper electrode layers and lower electrode layers laid out in a matrix are deposited with a ferroelectric layer therebetween, and a plurality of ferroelectric capacitors are provided at each intersection of the upper electrode layers and the lower electrode layers. See, for example, Japanese Unexamined Patent Application Publication No. 9-116107.
Referring to FIG. 5, a widely used method for manufacturing such a cross-point FeRAM will now be described. FIG. 5 is a sectional view illustrating steps of a conventional method for manufacturing a semiconductor device.
Initially, a lower electrode layer forming film (not shown in the drawing), a ferroelectric layer forming film (not shown in the drawing), and an upper electrode supporting layer forming film 200c are provided in this order by using a known sputtering method on the upper surface of an interlayer insulating layer formed on a semiconductor substrate on which a MOS transistor or the like have been provided in a step not being illustrated in the drawing. As shown in FIG. 5(a), a lower electrode layer forming mask M100 on which a pattern for forming lower electrode layers in the column direction (in the horizontal direction of FIG. 5) has been formed can be deposited on the upper surface of the upper electrode supporting layer forming film 200c. 
Subsequently, as shown in FIG. 5(b), the upper electrode supporting layer forming film 200c, the ferroelectric layer forming film (not shown in the drawing), and the lower electrode layer forming film (not shown in the drawing) are removed all at once, except for regions where a lower electrode layer is to be formed, by using a known photolithography and etching technique. Thus, a multilayer for forming a capacitor made up of a lower electrode layer (not shown in the drawing), a ferroelectric layer (not shown in the drawing), and an upper electrode supporting layer 200C can be provided in multiple numbers only in the regions where a lower electrode layer is to be formed on an interlayer insulating layer 100.
Next, as shown in FIG. 5(c), an insulating layer 300 is provided on the whole upper surface of the interlayer insulating layer, where the multilayer for forming a capacitor is provided in the regions where a lower electrode layer is to be formed, by using a known chemical vapor deposition (CVD) method.
Then the whole upper surface of the insulating layer 300 is planarized by a known etchback or chemical mechanical polishing (CMP) method. Subsequently, a via hole V100 is formed reaching from the upper surface of the insulating layer 300 to the upper surface of the upper electrode supporting layer 200C, where a ferroelectric capacitor C is to be formed.
Subsequently, as shown in FIG. 5(d), an upper electrode layer forming film (not shown in the drawing) is provided on the whole upper surface of the insulating layer 300, where the via hole V100 is formed, by using a known sputtering method. Then an upper electrode layer 200D is provided in multiple numbers in the row direction (in the vertical direction of FIG. 5) in regions where the upper electrode is to be formed, including the regions where the ferroelectric capacitor C is to be formed, by using a known photolithography and etching technique. Of the multilayer for forming a capacitor, the upper electrode supporting layer 200C here is removed by etching to form the upper electrode layer forming film except for the regions where the ferroelectric capacitor C is to be formed, and thereby a ferroelectric layer 200B on a lower electrode layer 200A can be exposed.
Thus, the upper electrode layer 200D and the lower electrode layer 200A, provided in multiple numbers in a matrix, are deposited with the ferroelectric layer 200B and the upper electrode supporting layer 200C therebetween, and the ferroelectric capacitor C is provided in multiple numbers, each provided at an intersection of the upper electrode layer 200D and the lower electrode layer 200A.